1. Field of the Invention
The present invention relates generally to insulated gate field effect semiconductor devices and more specifically to insulated gate field effect transistors (IGFETs), silicon controlled rectifiers (SCRS), insulated gate bipolar transistors (IGBTs) and the like. More particularly, the invention relates to vertical planar and non-planar devices of the double-diffused MOS (DMOS) variety, and still more particularly to the class of such devices adapted for use in applications requiring high power handling capabilities.
2. Description of the Background Art
Vertical insulated gate field effect semiconductor devices such as IGFETs, IGBTs and SCRs are commonly used to perform high power switching functions in power supply, automotive and other applications. Insulated gate field effect devices are generally characterized by very high input impedance, low turn-on or threshold voltages, and resistance to thermal effects, which are desirable in such applications, and which generally distinguish them from bipolar devices.
In designing such devices for high power switching applications, it is desirable to maximize the current carrying capacity in the forward conductance ("on") mode while simultaneously maximizing the breakdown voltage level in the blocking ("off") mode.
To achieve the first objective, it is important to maximize the number of discrete current-conducting cells comprising the device. At the same time, it is desirable to shrink the cell dimensions as much as possible in order to reduce the size of the silicon chip in which they are formed and hence reduce the cost per device. Today's IGFETs, for example, commonly contain as many as 100,000-250,000 discrete current-conducting transistor cells operating in parallel to carry currents as high as 50-100 amperes in dice ranging from about 50-300 square mils in size.
The second objective is generally achieved by suitable selection of the resistivity and thickness dimension of the drift or drain region, which in vertical devices is typically epitaxially grown on a low resistivity substrate. In addition, it is desirable to design cell structures which distribute or shape the concentration of the electric field in the blocking mode so that under drain avalanche conditions problems such as activation of parasitic devices and damage to dielectric layers are avoided.
Drain avalanche breakdown typically occurs under conditions of high reverse drain-source voltage. Under such conditions, impact ionization generates avalanche current carriers, i.e., holes or electrons, in the device. The avalanche current flow is concentrated in areas of high electrical field intensity. Although the drain avalanche condition may occur under the application of steady state drain-source voltages, it most commonly occurs as a result of very high transient voltages, for example in switching applications involving unclamped inductive loads.
IGFETs in particular are generally subject to two major failure mechanisms under avalanche breakdown conditions. The first failure mechanism is a result of avalanche initialization around the peripheral areas of the device, which ultimately leads to localized thermal failure around the periphery or termination regions. This mechanism has been addressed by special structural designs which redistribute the electric field and determine the avalanche initialization away from the periphery and into the active cell region of the device. For example, it has been common to employ one or more field rings or field plates in the vicinity of the periphery.
The second major failure mechanism results from avalanche current generation in the active cell region and its effect on the parasitic bipolar transistor which is inherent in IGFETs, and particularly in metal oxide silicon FETs (MOSFETs). All MOSFETs have a parasitic bipolar transistor which comprises the adjacent source, body, and drain regions of the MOSFET. Under drain avalanche conditions, impactionization generated carriers may be injected laterally into the base region of the parasitic bipolar, i.e., the body region of the MOSFET beneath the source. This portion of the body region is typically relatively lightly doped and thus has relatively high resistivity. The lateral flow of avalanche current through the region thus produces a voltage drop across the parasitic bipolar base-emitter junction. When the base current reaches a point where the base-emitter voltage drop exceeds the turn-on voltage of the junction (about 0.7 volts in silicon), the parasitic bipolar turns "on" and begins to conduct current between its collector (the MOSFET drain) and its emitter (the MOSFET source). If not prevented or limited, this leads to a "latch-up" condition in which current flows directly between the MOSFET source and drain. Operationally this is an undesirable result because gate control of the MOSFET is lost.
In addition to maximizing the breakdown voltage of the device, it is also highly desirable to maximize the "ruggedness" of the device, i.e., its ability to withstand avalanche breakdown conditions without being damaged or destroyed. Heretofore, semiconductor device designers have attempted to achieve this feature by designing cell structures to redistribute the electric field and redirect the avalanche current flow within the active cell region, and to resist activation of the parasitic bipolar transistor, while maintaining relatively small cell dimensions. The attempts of which applicants are aware have been less than completely successful in providing devices which are rugged and which simultaneously retain the other desirable electrical characteristics of this class of devices.
For example, vertical DMOS FET cell designs have been proposed in which the body in the central region of the cell, away from the gate-channel region, is characterized by a deep, heavily-doped portion, whereas the region of the body underlying and adjacent to the source, channel and gate is more lightly doped. The so-called "deep-body" cell design, which is disclosed in U.S. Pat. Nos. 4,642,666 and 4,705,759 to Lidow et al., is intended to redirect avalanche breakdown current to the deep body portion and away from the source, gate and channel regions.
The "deep-body" cell design has certain short-comings. The deep-body dopant is introduced relatively early in the fabrication process and it is difficult to control the lateral diffusion of the heavily doped central body region during subsequent fabrication steps. Lateral diffusion of the deep-body dopant into the channel region can easily occur, resulting in an attendant and undesirable increase in the turn-on threshold of the device. This consequence can be avoided if the lateral dimensions of the cell are maintained relatively large. However, this in turn reduces the number of cells which can be fabricated on a die of a given size and therefore reduces the forward current carrying capacity of the device for a given die size. Moreover, the "deep-body" cell design generally requires a relatively thick drain to accommodate the relatively deep vertical diffusion of the deep-body dopant. Thus, the "deep-body" design is essentially limited to use in relatively large devices rated for very high breakdown voltages.
It has also been proposed to use a highly-doped "shallow-body" in the central cell region of the body. The so-called "shallow-body" cell design is disclosed in U.S. Pat. No. 4,974,059 issued to Kinzer et al. In this design, the highly-doped shallow-body region extends from the central cell region and beneath the source region. It is intended to inhibit turn-on of the parasitic bipolar transistor by increasing the doping concentration of the base region and thus reducing its resistivity. This in turn requires the base current to be higher to forward bias the base-emitter junction and turn-on the parasitic bipolar. While the shallow-body cell design improves upon the deep-body design in certain respect, it too has certain short-comings. Because the shallow-body is shallow, its periphery exhibits a relatively sharp curvature beneath the source. This relatively sharp curvature tends to intensify the electric field in that region. Thus, under avalanche breakdown conditions, avalanche current will tend to flow heavily in that region because the electric field is most intense there. Simulations have shown that the shallow-body design is not effective in preventing avalanche current flow into the base of the parasitic bipolar, but only requires a greater current flow to turn-on the parasitic bipolar. Therefore, when the parasitic bipolar does turn on, it turns on at a higher avalanche current. The so-called "shallow-body" design has thus been shown to improve device ruggedness, but not to completely eliminate turn-on of the parasitic bipolar.
It is therefore an object of the present invention to overcome these and other short-comings of prior art cell designs by means of a cell design strategy for insulated gate semiconductor devices which employs strategically placed, highly-doped implant regions, which significantly improve device ruggedness.
It is a further object of the invention to improve upon the prior art cell designs by strategically locating and tailoring highly-doped implant regions to effectively reshape the electric field structure and to redirect avalanche breakdown current flow toward the central cell region and away from the insulated gate, channel and source regions.
It is still a further object of the invention to employ strategically placed and tailored highly-doped implant regions to redirect avalanche current flow away from the base of the parasitic bipolar transistor inherent in MOSFETs and to thereby prevent activation of the parasitic bipolar under an avalanche breakdown condition.
It is another object of the invention to provide the foregoing improvements in a way that is consistent with shrinkage of cell dimensions in order to allow packing more cells per unit area of semiconductor die and to thus improve the current per area carrying capacities of insulated gate semiconductor devices employing the invention.
It is still a further object of the invention to provide the foregoing improvements with little or no impact on critical electrical characteristics of existing devices, such as breakdown voltage and turn-on threshold, and with minimal impact on conventional fabrication processes.